Mechanisms for preventing the accumulation of electrostatic charge on integrated circuits, particularly MOS devices, are well documented in the literature. Typically, protection against electrostatic breakdown is accomplished by incorporating some form of threshold sensitive circuit (e.g. breakdown diodes, parasitic transistors) into the (silicon) substrate upstream of the component (e.g. the gate of an FET) to be protected, which serves to shunt what would otherwise be a potentially damaging current spike (caused by electrostatic charge buildup on interconnect metal) through the (resistive) substrate to a reference potential (usually the power supply potentials that are effectively tied off through the substrate).
In a GaAs-resident integrated circuit, however, because the substrate is semi-insulative, the convenience of (large area) current shunting PN junctions in a resistive substrate is not available for discharging electrostatic build-up on (gate) interconnect metal. As a consequence it has become common practice to form a Schottky barrier layer in a portion of the GaAs substrate adjacent to the input metal and tie together the cathode regions, which are spaced apart on opposite sides of the Schottky defining anode region. With the input metal connected to the anode region electrostatic charge is diverted away through the Schottky region. Unfortunately, the current carrying capacity of this approach is relatively small, so that it is not uncommon for a discharge arc to occur between the anode metal and the cathode connection metal. Furthermore, to limit (clamp) the current on the input metal a resistor is often coupled in series with the input metal and the component to be protected. Because of the non-negligible parasitic capacitance of the Schottky regions and the presence of the input clamping resistor, input signals to the circuit now encounter a substantial RC delay penalty, which limits the performance of the circuit.